]> git.baikalelectronics.ru Git - kernel.git/commit
projects / kernel.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 0d9ee07) | patch
powerpc/perf: Add missing L2 constraint handling in Power7 PMU
authorMichael Ellerman <michael@ellerman.id.au>
Tue, 30 Oct 2012 16:09:56 +0000 (16:09 +0000)
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>
Thu, 15 Nov 2012 02:00:36 +0000 (13:00 +1100)
commit8224fef03e30564ea3e0317f2c0609ad29b05d4b
tree4854509b69457adb40f1a82fb853920208c99238tree | snapshot
parent0d9ee07692a302360eb029e8fbf9525e0805838ecommit | diff
powerpc/perf: Add missing L2 constraint handling in Power7 PMU

If we have two cache events that require different settings of the L2SEL
bits in MMCR1 then we can not schedule those events simultaneously. Add
logic to the constraint handling to express that.

Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Acked-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
arch/powerpc/perf/power7-pmu.c diff | blob | history
Linux Kernel Source Tree.