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clk: sunxi: add PLL5 and PLL6 support
authorEmilio López <emilio@elopez.com.ar>
Mon, 23 Dec 2013 03:32:37 +0000 (00:32 -0300)
committerEmilio López <emilio@elopez.com.ar>
Sat, 28 Dec 2013 20:08:17 +0000 (17:08 -0300)
commit80e1c30749adb5a0b010ed388ead6187a82631d6
tree7c1d6a78ae45ac0aed61a96ae856f9cd295f70a3tree | snapshot
parent086a67d547ba0e3ed2c0d727ab02c04b9ca837a4commit | diff
clk: sunxi: add PLL5 and PLL6 support

This commit implements PLL5 and PLL6 support on the sunxi clock driver.
These PLLs use a similar factor clock, but differ on their outputs.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Mike Turquette <mturquette@linaro.org>
Documentation/devicetree/bindings/clock/sunxi.txt diff | blob | history
drivers/clk/sunxi/clk-sunxi.c diff | blob | history
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