git.baikalelectronics.ru Git - uboot.git/commit

]> git.baikalelectronics.ru Git - uboot.git/commit

author	Bin Meng <bmeng@tinylab.org>
	Wed, 21 Jun 2023 15:11:46 +0000 (23:11 +0800)
committer	Leo Yu-Chi Liang <ycliang@andestech.com>
	Wed, 12 Jul 2023 05:21:40 +0000 (13:21 +0800)
commit	7e9b17164391f490c8fffbdb628f2eb7941e18c0
tree	45a6e78f33e00d2a1bbe996d5895162c7f9dbf05	tree \| snapshot
parent	5314dec1cd4841a3f2607e3526cc6360f15c46e2	commit \| diff

riscv: Rename SiFive CLINT to RISC-V ALINT

As the RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V
ALINT in the source tree to be future-proof.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>

16 files changed:

MAINTAINERS		diff \| blob \| history
arch/riscv/Kconfig		diff \| blob \| history
arch/riscv/cpu/fu540/Kconfig		diff \| blob \| history
arch/riscv/cpu/fu740/Kconfig		diff \| blob \| history
arch/riscv/cpu/generic/Kconfig		diff \| blob \| history
arch/riscv/cpu/jh7110/Kconfig		diff \| blob \| history
arch/riscv/include/asm/global_data.h		diff \| blob \| history
arch/riscv/include/asm/syscon.h		diff \| blob \| history
arch/riscv/lib/Makefile		diff \| blob \| history
arch/riscv/lib/aclint_ipi.c	[new file with mode: 0644]	blob
arch/riscv/lib/sifive_clint.c	[deleted file]	blob \| history
board/openpiton/riscv64/Kconfig		diff \| blob \| history
board/sipeed/maix/Kconfig		diff \| blob \| history
drivers/timer/Makefile		diff \| blob \| history
drivers/timer/riscv_aclint_timer.c	[new file with mode: 0644]	blob
drivers/timer/sifive_clint_timer.c	[deleted file]	blob \| history

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