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clk: renesas: r9a07g044: Add GbEthernet clock/reset
authorBiju Das <biju.das.jz@bp.renesas.com>
Wed, 22 Sep 2021 15:51:45 +0000 (16:51 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Fri, 24 Sep 2021 13:11:05 +0000 (15:11 +0200)
commit7e8dafe3d24f019660359fdd99b7af2dad6be4f2
treed96123d909a0ae76a15cbef9f2c5bdf727b3899ftree | snapshot
parent3e8b74f28ede28c5e66c74793e7ec2f8e18e4baecommit | diff
clk: renesas: r9a07g044: Add GbEthernet clock/reset

Add ETH{0,1} clock/reset entries to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210922155145.28156-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a07g044-cpg.c diff | blob | history
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