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ath9k: Fix ack SIFS time for quarter/half channels
authorWojciech Dubowik <Wojciech.Dubowik@neratec.com>
Tue, 20 Feb 2018 14:42:00 +0000 (15:42 +0100)
committerKalle Valo <kvalo@codeaurora.org>
Tue, 27 Feb 2018 16:47:29 +0000 (18:47 +0200)
commit7d5d9ea49b653684b7b6860419c4ee9742416f6b
tree6a0a15e71e80b049b17f923ae17bb70226888af3tree | snapshot
parentd4cbdfb2a4727bfdde3c39f7d9e81b329eba93bacommit | diff
ath9k: Fix ack SIFS time for quarter/half channels

Ack timing generation has to be adapted for 5/10 MHz channels.
Do it by properly initializing ack shift field in TXSIFS
register. Ack shift assumes channel width of 2.5 Mhz so
value zero means 2.5 MHz, 1 is 5 MHz and so on.

Signed-off-by: Wojciech Dubowik <Wojciech.Dubowik@neratec.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
drivers/net/wireless/ath/ath9k/hw.c diff | blob | history
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