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(parent: 52190e7) | patch
drm/radeon/kms: properly set the CLK_REF bit for DCE3 devices
authorAlex Deucher <alexdeucher@gmail.com>
Fri, 20 May 2011 16:36:12 +0000 (12:36 -0400)
committerDave Airlie <airlied@gmail.com>
Sun, 22 May 2011 10:20:05 +0000 (20:20 +1000)
commit7b1e4c5e18ca83b6d60f69d9ed596c97e42f4eef
tree014495d41f3db1388f08412a4d690267b95bf99etree | snapshot
parent52190e7748f544411748413a3795f6e643953ef0commit | diff
drm/radeon/kms: properly set the CLK_REF bit for DCE3 devices

If the ss clock is external, the CLK_REF bit needs to be set
in the SetPixelClock parameters.  This should fix DP failures
in the channel equalization loop.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@gmail.com>
drivers/gpu/drm/radeon/atombios_crtc.c diff | blob | history
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