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(parent: e18dae5) | patch
drm/i915: Fix VLV eDP timing v2
authorChon Ming Lee <chon.ming.lee@intel.com>
Wed, 25 Sep 2013 07:47:51 +0000 (15:47 +0800)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 1 Oct 2013 05:45:22 +0000 (07:45 +0200)
commit71fc93177e04e91332fee7025db4aaa56f626acf
treead65a36cbff69bd5c7e2760f6998f98d08c4d9catree | snapshot
parente18dae5e90cb429cc5a4e21b4be45ec32cc38ce4commit | diff
drm/i915: Fix VLV eDP timing v2

Fix the typo in previous commit for DP 1.62 divisor.
drm/i915: Move Valleyview DP DPLL divisor calc to intel_dp_set_clock v2

v2: sigh, the m1 div is 3.

Reported-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_dp.c diff | blob | history
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