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(parent: 4582f18) | patch
clk: sunxi-ng: a83t: Add M divider to TCON1 clock
authorJernej Škrabec <jernej.skrabec@siol.net>
Sat, 30 Dec 2017 21:01:54 +0000 (22:01 +0100)
committerChen-Yu Tsai <wens@csie.org>
Wed, 3 Jan 2018 05:45:04 +0000 (13:45 +0800)
commit719555cb9a0b76f00c718da0a69e83b6f76fab64
tree0e8b3a79fe339717b8aea4ceae21e479576f7877tree | snapshot
parent4582f18580767d580821f3d455fcf4a2bb13a435commit | diff
clk: sunxi-ng: a83t: Add M divider to TCON1 clock

TCON1 also has M divider, contrary to TCON0. And the mux is only
2 bits wide, instead of 3.

Fixes: d84dbeee653f ("clk: sunxi-ng: Add driver for A83T CCU")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
[wens@csie.org: Add description about mux width difference]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
drivers/clk/sunxi-ng/ccu-sun8i-a83t.c diff | blob | history
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