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(parent: ce88222) | patch
drm/tegra: dpaux: Fix transfers larger than 4 bytes
authorThierry Reding <treding@nvidia.com>
Thu, 11 Jun 2015 16:33:48 +0000 (18:33 +0200)
committerThierry Reding <treding@nvidia.com>
Fri, 12 Jun 2015 14:22:46 +0000 (16:22 +0200)
commit6fcb8e8d678766d6b59c2e04b2c26d9281809a2f
treec71bc338728059b18bfd0f031956fbb73e288751tree | snapshot
parentce88222e1fb53c38d3b94c3b5ceebe1d2ab4956dcommit | diff
drm/tegra: dpaux: Fix transfers larger than 4 bytes

The DPAUX read/write FIFO registers aren't sequential in the register
space, causing transfers larger than 4 bytes to cause accesses to non-
existing FIFO registers.

Fixes: ec19c5b9f9d1 ("drm/tegra: Add eDP support")
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/gpu/drm/tegra/dpaux.c diff | blob | history
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