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iio: adc: ad7280a: Fix alignment for DMA safety
authorJonathan Cameron <Jonathan.Cameron@huawei.com>
Sun, 8 May 2022 17:55:50 +0000 (18:55 +0100)
committerJonathan Cameron <Jonathan.Cameron@huawei.com>
Tue, 14 Jun 2022 10:53:12 +0000 (11:53 +0100)
commit6f3bc54b90d8acae9c0753704f2346d7714feb7b
tree32062d2a709a7f42d31b99f5b9b2f5fe1faf1f54tree | snapshot
parent5940701df355ce250edc4f29b33b7fd3033a4455commit | diff
iio: adc: ad7280a: Fix alignment for DMA safety

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Fixes: b2c946ca1e00 ("staging:iio:adc:ad7280a: Split buff[2] into tx and rx parts")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-11-jic23@kernel.org
drivers/iio/adc/ad7280a.c diff | blob | history
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