]> git.baikalelectronics.ru Git - uboot.git/commit
rockchip: clk: Add SARADC clock support for rk3288
authorDavid Wu <david.wu@rock-chips.com>
Wed, 20 Sep 2017 06:28:19 +0000 (14:28 +0800)
committerPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Sat, 30 Sep 2017 22:33:29 +0000 (00:33 +0200)
commit67bd451f9a7d80a70e4baf1da0ab4dfb02360266
tree57fba8ac99e6c10b3ab505c6e8ded1637e850706
parent633f5ed54ffc30d433d1d32a1389f8c4da6073b0
rockchip: clk: Add SARADC clock support for rk3288

The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
drivers/clk/rockchip/clk_rk3288.c