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(parent: 7e6cd33) | patch
drm/i915: Set PIPECONF color range bit on Valleyview
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Tue, 2 Apr 2013 13:10:09 +0000 (16:10 +0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 5 Apr 2013 18:47:20 +0000 (20:47 +0200)
commit65651ec95db87f12e44087e215efe3763b6b7674
treebb3d1dd24b775960ab4dc554ce93e7f56e37d536tree | snapshot
parent7e6cd3363bc5a9326ae3c5d9782bb7295573280dcommit | diff
drm/i915: Set PIPECONF color range bit on Valleyview

VLV has the color range selection bit in the PIPECONF register.
Configure it appropriately.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
[danvet: fixup rebase issues due to slightly different baseline.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_display.c diff | blob | history
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