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(parent: 8e7f220) | patch
x86: Reduce mrccache record alignment size
authorSimon Glass <sjg@chromium.org>
Sat, 7 Dec 2019 04:42:01 +0000 (21:42 -0700)
committerBin Meng <bmeng.cn@gmail.com>
Sun, 15 Dec 2019 03:44:12 +0000 (11:44 +0800)
commit64829f9b286af5935a0c403f7a80cc6f11af870f
treeaad889f23a3c1c6937d43050c99847e7783c9163tree | snapshot
parent8e7f220f2128288153d1e4f725380da7712bd5e8commit | diff
x86: Reduce mrccache record alignment size

At present the records are 4KB in size. This is unnecessarily large when
the SPI-flash erase size is 256 bytes. Reduce it so it will be more
efficient with Apollo Lake's 24-byte variable-data record.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
arch/x86/include/asm/mrccache.h diff | blob | history
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