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(parent: dc3b9d1) | patch
clk: samsung: exynosautov9: add fsys0 clock support
authorChanho Park <chanho61.park@samsung.com>
Fri, 29 Jul 2022 00:30:23 +0000 (09:30 +0900)
committerKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Tue, 23 Aug 2022 06:21:35 +0000 (09:21 +0300)
commit647216d029a804e9d7305f41ef7f9b1f1cf0b871
treeb569da36e6e5d19817c5937ac2e34e76747fbc82tree | snapshot
parentdc3b9d13ab9d1f7a706c683950278875ec94e0d1commit | diff
clk: samsung: exynosautov9: add fsys0 clock support

CMU_FSYS0 block provides clocks for PCIe Gen3 1 x 4Lanes and 2 x 2
Lanes.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/ae84d4a0487a5299076bfeef5732579f5207acf9.1659054220.git.chanho61.park@samsung.com
drivers/clk/samsung/clk-exynosautov9.c diff | blob | history
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