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(parent: 0105593) | patch
clk: renesas: rcar-gen3: Add workaround for PLL0/2/4 errata on H3 ES1.0
authorGeert Uytterhoeven <geert+renesas@glider.be>
Fri, 10 Mar 2017 10:46:10 +0000 (11:46 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 21 Mar 2017 10:12:23 +0000 (11:12 +0100)
commit62ad9efea6f37c77fcfafb981b9d131d21c37fda
tree70063577f87854f64623c482b7227ee3734810c2tree | snapshot
parent01055930b10e350dce79ee99e8628ed61653219acommit | diff
clk: renesas: rcar-gen3: Add workaround for PLL0/2/4 errata on H3 ES1.0

Add a workaround for errata on R-Car H3 ES1.0, where the PLL0, PLL2, and
PLL4 clock frequencies are off by a factor of two.

Inspired by a patch by Dien Pham in the BSP.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Dien Pham <dien.pham.ry@renesas.com>
drivers/clk/renesas/rcar-gen3-cpg.c diff | blob | history
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