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(parent: cce87f6) | patch
ddr: fsl: set cdr1 first in case 0.9v VDD is enabled for some SoCs
authorRajesh Bhagat <rajesh.bhagat@nxp.com>
Wed, 17 Jan 2018 10:43:06 +0000 (16:13 +0530)
committerYork Sun <york.sun@nxp.com>
Tue, 23 Jan 2018 19:20:03 +0000 (11:20 -0800)
commit5fcc65a723ba1adc658b812ab5754cd88aac9c9e
tree32f7d0ba67574dbb9c660935008e0abcf9743f7btree | snapshot
parentcce87f6713e91a957819ed6ff16b2d5af4a9be50commit | diff
ddr: fsl: set cdr1 first in case 0.9v VDD is enabled for some SoCs

Sets DDR configuration parameter cdr1 before all other settings
to support case 0.9v VDD is enabled for some SoCs

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
drivers/ddr/fsl/fsl_ddr_gen4.c diff | blob | history
"Das U-Boot" Source Tree.