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(parent: bc8745d) | patch
ARM: OMAP4: Make L4SEC clock domain SWSUP only
authorTero Kristo <t-kristo@ti.com>
Wed, 29 Apr 2020 14:30:01 +0000 (17:30 +0300)
committerTony Lindgren <tony@atomide.com>
Tue, 5 May 2020 18:16:06 +0000 (11:16 -0700)
commit5ade2ce6a4179d28469ea781b89dbd681b570fdb
treeee4b76632fba4929e66eac9d22cbfdcdeba68d99tree | snapshot
parentbc8745d60e6101ea1b368d4ec7dc845e6068674ecommit | diff
ARM: OMAP4: Make L4SEC clock domain SWSUP only

Commit e9cf4827c000 ('ARM: OMAP: DRA7xx: Make L4SEC clock domain SWSUP
only') made DRA7 SoC L4SEC clock domain SWSUP only because of power
state transition issues detected with HWSUP mode. Based on
experimentation similar issue exists on OMAP4, so do the same change
for OMAP4 also.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
arch/arm/mach-omap2/clockdomains44xx_data.c diff | blob | history
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