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(parent: 6110a7a) | patch
spi: rockchip: Set rx_fifo interrupt waterline base on transfer item
authorJon Lin <jon.lin@rock-chips.com>
Mon, 21 Jun 2021 10:47:57 +0000 (18:47 +0800)
committerMark Brown <broonie@kernel.org>
Wed, 23 Jun 2021 11:35:41 +0000 (12:35 +0100)
commit58db9a89a2fefee68ed12cfe4aba18f4355d7de3
tree1ff7c9f09dfa4ab09d9f4e165104328b44e327cbtree | snapshot
parent6110a7aec78e4333bd5a3a7fc7eab4056121a6cfcommit | diff
spi: rockchip: Set rx_fifo interrupt waterline base on transfer item

The error here is to calculate the width as 8 bits. In fact, 16 bits
should be considered.

Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Link: https://lore.kernel.org/r/20210621104800.19088-4-jon.lin@rock-chips.com
Signed-off-by: Mark Brown <broonie@kernel.org>
drivers/spi/spi-rockchip.c diff | blob | history
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