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(parent: ae6129b) | patch
drm/tegra: dpaux: Registers are 32-bit
authorThierry Reding <treding@nvidia.com>
Tue, 2 Jun 2015 11:13:01 +0000 (13:13 +0200)
committerThierry Reding <treding@nvidia.com>
Fri, 12 Jun 2015 14:26:04 +0000 (16:26 +0200)
commit569176c66c89d0fe7817fc426960cd310c04b6af
tree4bb8b985a8c62ad80e531d8aa393a368546510fftree | snapshot
parentae6129bd194c83c20d98936ec57f9fc36116f320commit | diff
drm/tegra: dpaux: Registers are 32-bit

Use a sized unsigned 32-bit data type (u32) to store register contents.
The DPAUX registers are 32 bits wide irrespective of the architecture's
data width.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/gpu/drm/tegra/dpaux.c diff | blob | history
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