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ARM: at91: ma5d4: Switch DDR2 controller to sequencial address decoding
authorMarek Vasut <marex@denx.de>
Tue, 2 May 2017 18:27:41 +0000 (20:27 +0200)
committerTom Rini <trini@konsulko.com>
Thu, 29 Jun 2017 17:30:28 +0000 (13:30 -0400)
commit55ee9c816586fa981dd5403d7da14249bd6780aa
tree943eb63d7f3989a5eaa893019e516bf5209d5404tree | snapshot
parent08bd7463f1bba9c3fdf0ed46d25c7cbb4a49b5d6commit | diff
ARM: at91: ma5d4: Switch DDR2 controller to sequencial address decoding

According to the datasheet, sequential mapping is used for DDR
SDRAM, while interleaved mapping is used for regular SDRAM.
Incorrect configuration of this bit does indeed cause sporadic
memory instability.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Wenyou Yang <wenyou.yang@atmel.com>
board/aries/ma5d4evk/ma5d4evk.c diff | blob | history
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