]> git.baikalelectronics.ru Git - uboot.git/commit
drivers/ddr/fsl: Modify binding registers to save time on data init
authorYork Sun <york.sun@nxp.com>
Mon, 29 Jan 2018 17:44:37 +0000 (09:44 -0800)
committerYork Sun <york.sun@nxp.com>
Tue, 30 Jan 2018 17:14:07 +0000 (09:14 -0800)
commit551986b253b8b00818ef970a44ef4a968b72c6ae
tree1051b0488ab50a39badc166d44920d15f58bbd02
parentff4e1ae9e706e2e35594cca2b860496d1dc936ca
drivers/ddr/fsl: Modify binding registers to save time on data init

DDR controllers always use binding register to determine the memory
space to perform data initialization. In case of controller interleaving,
the space is doubled, resulting twice long wait. It wasn't too bad until
the memory capacity increases. To reduce the wait time, reduce the
binding space to half and restore it after data initialization.
Three-way interleaving is no longer used and is removed.

Signed-off-by: York Sun <york.sun@nxp.com>
drivers/ddr/fsl/fsl_ddr_gen4.c