drm/vc4: hvs: Correct interrupt masking bit assignment for HVS5

drm/vc4: hvs: Correct interrupt masking bit assignment for HVS5

[ Upstream commit ca3f8b02f8a92cb32f895a92a78b4e0ea5f54549 ]

HVS5 has moved the interrupt enable bits around within the
DISPCTRL register, therefore the configuration has to be updated
to account for this.

Fixes: 0d1c2ca1b0b0 ("drm/vc4: Add support for the BCM2711 HVS5")
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Link: https://lore.kernel.org/r/20221207-rpi-hvs-crtc-misc-v1-4-1f8e0770798b@cerno.tech
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Signed-off-by: Sasha Levin <sashal@kernel.org>