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KVM: PPC: Book3S PR: Emulate TIR register
authorAlexander Graf <agraf@suse.de>
Fri, 25 Apr 2014 14:07:21 +0000 (16:07 +0200)
committerAlexander Graf <agraf@suse.de>
Fri, 30 May 2014 12:26:22 +0000 (14:26 +0200)
commit50f14b14ee892b8e41f20667f0685507d47cd1f6
tree228059928f720af84ba0a9211eee2bf557e238eetree | snapshot
parent71064d96aa6a14f2bb9be18dfc4b92b05d691786commit | diff
KVM: PPC: Book3S PR: Emulate TIR register

In parallel to the Processor ID Register (PIR) threaded POWER8 also adds a
Thread ID Register (TIR). Since PR KVM doesn't emulate more than one thread
per core, we can just always expose 0 here.

Signed-off-by: Alexander Graf <agraf@suse.de>
arch/powerpc/kvm/book3s_emulate.c diff | blob | history
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