clk: renesas: r9a07g044: Add mux and divider for G clock

clk: renesas: r9a07g044: Add mux and divider for G clock

G clock is sourced from PLL3 and PLL6. The output of the mux is
connected to divider.

This patch adds a mux and divider for getting different rates from
this clock sources.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211203115154.31864-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>