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clk: renesas: r8a779f0: Add SDH0 clock
authorWolfram Sang <wsa+renesas@sang-engineering.com>
Mon, 11 Jul 2022 13:46:54 +0000 (15:46 +0200)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 15 Aug 2022 09:08:54 +0000 (11:08 +0200)
commit4ac19b7be5627f23e74046e755bfdab879ff5da9
tree888a3f5c6c7e1fa9538d4c78cce0236ac2f52abftree | snapshot
parent3d7dcb2c5450a57f60c448f42be48fdfe456bfdfcommit | diff
clk: renesas: r8a779f0: Add SDH0 clock

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20220711134656.277730-2-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r8a779f0-cpg-mssr.c diff | blob | history
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