git.baikalelectronics.ru Git - kernel.git/commit

author	Alex Deucher <alexdeucher@gmail.com>
	Fri, 20 May 2011 08:34:17 +0000 (04:34 -0400)
committer	Dave Airlie <airlied@redhat.com>
	Fri, 20 May 2011 10:02:22 +0000 (20:02 +1000)
commit	486eec63c70318341ff38c9dd83f37cfc993a247
tree	5f18745f77235b364f85c8b74804957b285cca4e	tree \| snapshot
parent	a605fb8e448967be6994097948b474a7888be540	commit \| diff

drm/radeon/kms: fix up DP clock programming on DCE4/5

In DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
depending on the asic. The crtc virtual pixel clock is derived from
the DP ref clock.

- DCE4: PPLL or ext clock
- DCE5: DCPLL or ext clock

Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
PPLL/DCPLL programming and only program the DP DTO for the
crtc virtual pixel clock.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

drivers/gpu/drm/radeon/atombios_crtc.c		diff \| blob \| history
drivers/gpu/drm/radeon/radeon_encoders.c		diff \| blob \| history