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(parent: 6b4e66f) | patch
drm/i915/gt: Trim gen6 ppgtt updates to PD cachelines
authorChris Wilson <chris@chris-wilson.co.uk>
Thu, 5 Dec 2019 23:40:59 +0000 (23:40 +0000)
committerChris Wilson <chris@chris-wilson.co.uk>
Fri, 6 Dec 2019 08:53:31 +0000 (08:53 +0000)
commit434f6c06afe106c1fe14ed250e3db6a805518580
tree8b1be57a3c051e651ee0afef639d379d8f709d64tree | snapshot
parent6b4e66f0e0d3026d7e277ea477d4ac63a32bd95fcommit | diff
drm/i915/gt: Trim gen6 ppgtt updates to PD cachelines

It appears now that we have the ring TLB invalidation in place, we need
only update the page directory cachelines that we have altered. A great
reduction from rewriting the whole 2MiB ppgtt on every update.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191205234059.1010030-1-chris@chris-wilson.co.uk
drivers/gpu/drm/i915/i915_gem_gtt.c diff | blob | history
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