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clk: renesas: r9a07g044: Add entry for fixed clock P0_DIV2
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Mon, 19 Jul 2021 14:38:10 +0000 (15:38 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 26 Jul 2021 12:15:23 +0000 (14:15 +0200)
commit41e7849b910b6a67f0197fb5ed3fa41ff3a7bc4f
tree6f764e15316cb08aebfae30348766a06c9029f87tree | snapshot
parentd2b6d4f6364faa2572236cfdcc294f592a65c09dcommit | diff
clk: renesas: r9a07g044: Add entry for fixed clock P0_DIV2

Add entry for fixed core clock P0_DIV2 and assign LAST_DT_CORE_CLK
to R9A07G044_CLK_P0_DIV2.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210719143811.2135-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a07g044-cpg.c diff | blob | history
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