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(parent: d0808cf) | patch
drm/amdgpu: add TX_POWER_CTRL_1 macro definitions for NBIO IP v7.7.0
authorTim Huang <tim.huang@amd.com>
Mon, 15 Aug 2022 05:03:49 +0000 (13:03 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 22 Aug 2022 20:47:09 +0000 (16:47 -0400)
commit3e6ae384b13503a0761aa4b14e4aa8872914dbf7
tree7d74111fbffaf1bb28f68b553378f2d5dcbc3623tree | snapshot
parentd0808cf24eb56ab7459b0618f836dc2e52dbe09dcommit | diff
drm/amdgpu: add TX_POWER_CTRL_1 macro definitions for NBIO IP v7.7.0

Add the BIF0_PCIE_TX_POWER_CTRL_1 register offset and mask macro
definitions for AMD_CG_SUPPORT_BIF_LS.

Signed-off-by: Tim Huang <tim.huang@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_7_0_offset.h diff | blob | history
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_7_0_sh_mask.h diff | blob | history
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