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(parent: 27fd7cd) | patch
powerpc/tm: update comment about interrupt re-entrancy
authorNicholas Piggin <npiggin@gmail.com>
Fri, 28 Jun 2019 05:33:32 +0000 (15:33 +1000)
committerMichael Ellerman <mpe@ellerman.id.au>
Tue, 2 Jul 2019 11:39:49 +0000 (21:39 +1000)
commit3d91a40796503123cbe80e5a1a1c7d48837292e6
treeaae2e59629903f03e463e905cf59b3c2eb510288tree | snapshot
parent27fd7cd882fb6397e6770673213d7aa2561bd817commit | diff
powerpc/tm: update comment about interrupt re-entrancy

Since the system reset interrupt began to use its own stack, and
machine check interrupts have done so for some time, r1 can be
changed without clearing MSR[RI], provided no other interrupts
(including SLB misses) are taken.

MSR[RI] does have to be cleared when using SCRATCH0, however.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
arch/powerpc/kernel/tm.S diff | blob | history
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