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(parent: 4ed9bde) | patch
pci: fsl: Do not access PCI BAR0 register of PCIe Root Port
authorPali Rohár <pali@kernel.org>
Tue, 2 May 2023 17:53:57 +0000 (19:53 +0200)
committerTom Rini <trini@konsulko.com>
Wed, 3 May 2023 22:30:46 +0000 (18:30 -0400)
commit3d22a1a0f429f9024da1fc32c85815af201a7e7d
tree91aabfe75c3f94edc285f9a3922917bf1042901etree | snapshot
parent4ed9bde9dd866f2923300e36be085bcb62838935commit | diff
pci: fsl: Do not access PCI BAR0 register of PCIe Root Port

Freescale PCIe Root Port has PEXCSRBAR register at position of PCI BAR0.
PCIe Root Port does not have any PCIe memory, so returns zero when trying
to read from PCIe Root Port BAR0 and ignore any writes.

Signed-off-by: Pali Rohár <pali@kernel.org>
drivers/pci/pcie_fsl.c diff | blob | history
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