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(parent: 624b3b9) | patch
drm/amdgpu: Fix incorrect register offsets for Sienna Cichlid
authorRohit Khaire <rohit.khaire@amd.com>
Fri, 4 Jun 2021 15:02:56 +0000 (11:02 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 4 Jun 2021 20:02:44 +0000 (16:02 -0400)
commit3c28ac8c825ec8a234544f202a392fe3db2641f8
treeef6167ecd622656f0def728aa2f31636089e1c5dtree | snapshot
parent624b3b9e2db352b7a7f20619d8688b49ca1f9a58commit | diff
drm/amdgpu: Fix incorrect register offsets for Sienna Cichlid

RLC_CP_SCHEDULERS and RLC_SPARE_INT0 have different
offsets for Sienna Cichlid

Signed-off-by: Rohit Khaire <rohit.khaire@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c diff | blob | history
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