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(parent: cd33f34) | patch
drm/tegra: sor: Registers are 32-bit
authorThierry Reding <treding@nvidia.com>
Mon, 26 Jan 2015 15:02:48 +0000 (16:02 +0100)
committerThierry Reding <treding@nvidia.com>
Thu, 2 Apr 2015 16:46:16 +0000 (18:46 +0200)
commit3a3b8fe4aede3191a9fc7841e6dcc9b2cc213a3e
treed40639a99dc33d82b6586b2b27c68c36bac18d46tree | snapshot
parentcd33f345780b9ad0e4519cc8c4167fb05960bbf5commit | diff
drm/tegra: sor: Registers are 32-bit

Use a sized unsigned 32-bit data type (u32) to store register contents.
The SOR registers are 32 bits wide irrespective of the architecture's
data width.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/gpu/drm/tegra/sor.c diff | blob | history
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