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clk: renesas: r9a07g044: Fix P1 Clock
authorBiju Das <biju.das.jz@bp.renesas.com>
Sat, 26 Jun 2021 08:13:37 +0000 (09:13 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 12 Jul 2021 08:52:03 +0000 (10:52 +0200)
commit3a0812af2e61d851147825c0bda2df3d4633f159
tree1ff9d0af260d9b8086c8106b4af4d6ceb38bf82ctree | snapshot
parent6315d9405f39db19af3fbc9c8f2bdf6cbdf26065commit | diff
clk: renesas: r9a07g044: Fix P1 Clock

As per RZ/G2L HW Manual(Rev.0.50) P1 is sourced from pll3_div2_4.
So fix the clock definitions for P1.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210626081344.5783-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a07g044-cpg.c diff | blob | history
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