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feat(intel): setup FPGA interface for Agilex
authorJit Loon Lim <jit.loon.lim@intel.com>
Wed, 15 Jun 2022 12:59:33 +0000 (14:59 +0200)
committerSieu Mun Tang <sieu.mun.tang@intel.com>
Tue, 22 Nov 2022 15:35:36 +0000 (23:35 +0800)
commit3905f57134853f47f6e859b8b6322a7dbbfc49f7
tree45cbcba4efb3647a38d3a09ddabd1a3dc9543b39tree | snapshot
parente6c038909193b83bc293de9b1eb65440e75f8c91commit | diff
feat(intel): setup FPGA interface for Agilex

Enable/Disable FPGA interfaces based on handoff configuration.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I8667f362aa53e7c68723e0dbd5284844ae39dfb5
plat/intel/soc/agilex/include/agilex_pinmux.h diff | blob | history
plat/intel/soc/agilex/soc/agilex_pinmux.c diff | blob | history
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