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(parent: 044c034) | patch
drm/i915: Include TLB miss overhead for computing WM
authorChris Wilson <chris@chris-wilson.co.uk>
Sat, 8 Jan 2011 09:02:21 +0000 (09:02 +0000)
committerChris Wilson <chris@chris-wilson.co.uk>
Tue, 11 Jan 2011 20:44:54 +0000 (20:44 +0000)
commit38562d7daff05eec79d025837f11b365543cd352
treed16899c361fb77e7732eb603835cb95c3af49421tree | snapshot
parent044c034789c44646046a9e46e6c52c86a425e5e0commit | diff
drm/i915: Include TLB miss overhead for computing WM

The docs recommend that if 8 display lines fit inside the FIFO buffer,
then the number of watermark entries should be increased to hide the
latency of filling the rest of the FIFO buffer.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
drivers/gpu/drm/i915/intel_display.c diff | blob | history
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