git.baikalelectronics.ru Git - kernel.git/commit

]> git.baikalelectronics.ru Git - kernel.git/commit

author	Chao Peng <chao.p.peng@linux.intel.com>
	Wed, 24 Oct 2018 08:05:12 +0000 (16:05 +0800)
committer	Paolo Bonzini <pbonzini@redhat.com>
	Fri, 21 Dec 2018 10:28:35 +0000 (11:28 +0100)
commit	335a9b09ff0bfa72150c5dff473465d55b5cf09c
tree	1bdc097495a69ed493a21ef07cb07e77db0da902	tree \| snapshot
parent	d012e052be027869b50896c6daf4d6dd7346e475	commit \| diff

KVM: x86: Add Intel PT context switch for each vcpu

Load/Store Intel Processor Trace register in context switch.
MSR IA32_RTIT_CTL is loaded/stored automatically from VMCS.
In Host-Guest mode, we need load/resore PT MSRs only when PT
is enabled in guest.

Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
Signed-off-by: Luwei Kang <luwei.kang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

arch/x86/kvm/vmx/vmx.c		diff \| blob \| history
arch/x86/kvm/vmx/vmx.h		diff \| blob \| history

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