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(parent: 1b01924) | patch
CLK: HSDK: fix HDMI clock calculation
authorEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Wed, 29 Jan 2020 11:08:30 +0000 (14:08 +0300)
committerAlexey Brodkin <abrodkin@synopsys.com>
Wed, 12 Feb 2020 17:47:39 +0000 (20:47 +0300)
commit32fc90b9f0571aeca77f6e9fb3a293fbedcc0e58
tree0908b429e67d6bdd3e5732b64a2be9e82b1de37atree | snapshot
parent1b01924ef50a24b85e29684fb22d56e23cd13662commit | diff
CLK: HSDK: fix HDMI clock calculation

HDMI PLL has its own xtal with 27 MHz output but we treat it the same
way as other PLLs with 33.33 MHz input.
Fix that.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
drivers/clk/clk-hsdk-cgu.c diff | blob | history
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