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MIPS: features: Add initial support for Segmentation Control registers
authorSteven J. Hill <Steven.Hill@imgtec.com>
Thu, 14 Nov 2013 16:12:24 +0000 (16:12 +0000)
committerRalf Baechle <ralf@linux-mips.org>
Wed, 22 Jan 2014 19:18:58 +0000 (20:18 +0100)
commit2b79c7e9eb6585ede5c16be36935af9b6119619f
tree316ae10e4705f42a0690d44254be218c4bedbc03tree | snapshot
parente9c19f6e4d74f5e1bcbefe5d140d16b32140731fcommit | diff
MIPS: features: Add initial support for Segmentation Control registers

MIPS32R3 introduced a new set of Segmentation Control registers which
increase the flexibility of the segmented-based memory scheme.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6131/
arch/mips/include/asm/cpu-features.h diff | blob | history
arch/mips/include/asm/cpu.h diff | blob | history
arch/mips/include/asm/mipsregs.h diff | blob | history
arch/mips/kernel/cpu-probe.c diff | blob | history
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