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RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs
authorYash Shah <yash.shah@sifive.com>
Mon, 6 May 2019 10:48:40 +0000 (16:18 +0530)
committerPalmer Dabbelt <palmer@sifive.com>
Fri, 17 May 2019 03:42:13 +0000 (20:42 -0700)
commit28d33c564f45c375b185e0b45ab300f44a388108
treeeda00cc7ecc719a9ed5e9cb82d27b64fb929d4fatree | snapshot
parent74ab2d005fb1c389b8df6cf14c6a1165e730caeecommit | diff
RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs

The driver currently supports only SiFive FU540-C000 platform.

The initial version of L2 cache controller driver includes:
- Initial configuration reporting at boot up.
- Support for ECC related functionality.

Signed-off-by: Yash Shah <yash.shah@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
arch/riscv/include/asm/sifive_l2_cache.h [new file with mode: 0644] blob
arch/riscv/mm/Makefile diff | blob | history
arch/riscv/mm/sifive_l2_cache.c [new file with mode: 0644] blob
Linux Kernel Source Tree.