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(parent: 3207cc7) | patch
drm/radeon: put UVD PLLs in bypass mode
authorChristian König <christian.koenig@amd.com>
Thu, 18 Apr 2013 13:25:58 +0000 (15:25 +0200)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 22 Apr 2013 14:39:16 +0000 (10:39 -0400)
commit271de931b7f2c91cc1b0c6610590f2c96479fd8b
treed2f1500ca5a72b79d073770f28916d68d37a91fatree | snapshot
parent3207cc79d7cc3e98f2de5a958323ed804da00d77commit | diff
drm/radeon: put UVD PLLs in bypass mode

Just power down the PLL when we get a VCLK or DCLK of zero.
Enabling the bypass mode early should also allow us to
switch UVD clocks on the fly.

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/radeon/evergreen.c diff | blob | history
drivers/gpu/drm/radeon/rv770.c diff | blob | history
drivers/gpu/drm/radeon/si.c diff | blob | history
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