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(parent: d4f68ba) | patch
clk: clk_stm32f: Configure SAI PLL to generate LTDC pixel clock
authorPatrice Chotard <patrice.chotard@st.com>
Thu, 8 Feb 2018 16:20:49 +0000 (17:20 +0100)
committerTom Rini <trini@konsulko.com>
Wed, 14 Mar 2018 01:45:37 +0000 (21:45 -0400)
commit2191461bd3ebf647e75cc54f52da9a4add669a3a
tree95e115e585b41b95a80b4f702ecf1be2d7619896tree | snapshot
parentd4f68ba590fb774f3f09d2f325d54725d7c867d9commit | diff
clk: clk_stm32f: Configure SAI PLL to generate LTDC pixel clock

Configure SAI PLL configuration to generate LTDC pixel clock on
the PLLSAIR output.

PLLSAI is enabled only if CONFIG_VIDEO_STM32 flag is set.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
drivers/clk/clk_stm32f.c diff | blob | history
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