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spi: lantiq: Add fifo size bit mask in SoC specific data structure
authorDilip Kota <eswara.kota@linux.intel.com>
Fri, 17 Jul 2020 06:27:54 +0000 (14:27 +0800)
committerMark Brown <broonie@kernel.org>
Wed, 22 Jul 2020 00:55:57 +0000 (01:55 +0100)
commit218388df783c62d15da2a9811e00e18c6ec6508a
tree012e47018031f1412ca26d67126add81d684a0d6tree | snapshot
parent808ddd495e234f52977fefb08f071aa4b123e253commit | diff
spi: lantiq: Add fifo size bit mask in SoC specific data structure

On newer chipsets, SPI controller has fifos of larger size.
So add the fifo size bit mask entry in SoC specific data structure.

Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com>
Link: https://lore.kernel.org/r/a0889abf17a9fbc7077f10be0f0342b7ebdf9361.1594957019.git.eswara.kota@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
drivers/spi/spi-lantiq-ssc.c diff | blob | history
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