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(parent: fd52ef0) | patch
iio: adc: ti-ads8344: Fix alignment for DMA safety
authorJonathan Cameron <Jonathan.Cameron@huawei.com>
Sun, 8 May 2022 17:56:17 +0000 (18:56 +0100)
committerJonathan Cameron <Jonathan.Cameron@huawei.com>
Tue, 14 Jun 2022 10:53:15 +0000 (11:53 +0100)
commit203732ba786ca257184b21de3480f0f206602d2c
tree6100050194f387d70807de5c4e2e752020c1520etree | snapshot
parentfd52ef04b6d597e749e0168b00e26f99dc7ae923commit | diff
iio: adc: ti-ads8344: Fix alignment for DMA safety

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Fixes: f904e179a4d2 ("iio: adc: Add driver for the TI ADS8344 A/DC chips")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-38-jic23@kernel.org
drivers/iio/adc/ti-ads8344.c diff | blob | history
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