]> git.baikalelectronics.ru Git - kernel.git/commit
net/mlx5e: TX, Add geneve tunnel stateless offload support
authorMoshe Shemesh <moshe@mellanox.com>
Thu, 21 Mar 2019 22:51:38 +0000 (15:51 -0700)
committerSaeed Mahameed <saeedm@mellanox.com>
Fri, 22 Mar 2019 19:09:31 +0000 (12:09 -0700)
commit1fea449b59353a80066a265eea8d400cc85d7a9f
treeefbfd7befb33cc09e33ebd71d156011f1e42d9a4
parent9a540add966a03a31939b2c280c8f659d755ca70
net/mlx5e: TX, Add geneve tunnel stateless offload support

Currently support only default geneve udp port (6081).
For the tx side, the HW is assisted by SW parsing, which sets the
headers offset to offload tunneled LSO and csum. Note that for udp
tunnels, we don't use special rx offloads, as rss on the outer headers
is enough, we support checksum complete and GRO takes care of
aggregation.

Geneve TSO BW and CPU load results (tested using iperf single tcp
stream).
In this patch we add TSO support over Geneve, so the "before" result
doesn't actually get to using the TSO HW offload even when turned on.
Tested on ConnectX-5, Intel(R) Xeon(R) CPU E5-2660 v2 @2.20GHz.

 __________________________________
| Before         | After           |
|________________|_________________|
| 12.6 Gbits/sec | 21.7 Gbits/sec  |
| 100% CPU load  | 61.5% CPU load  |
|________________|_________________|

Signed-off-by: Moshe Shemesh <moshe@mellanox.com>
Acked-by: Or Gerlitz <ogerlitz@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
drivers/net/ethernet/mellanox/mlx5/core/en.h
drivers/net/ethernet/mellanox/mlx5/core/en_accel/en_accel.h
drivers/net/ethernet/mellanox/mlx5/core/en_main.c
drivers/net/ethernet/mellanox/mlx5/core/en_tx.c