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azure/gitlab/travis: Add RISC-V SPL testing
authorBin Meng <bmeng.cn@gmail.com>
Sat, 28 Mar 2020 14:25:29 +0000 (07:25 -0700)
committerTom Rini <trini@konsulko.com>
Fri, 10 Apr 2020 19:54:16 +0000 (15:54 -0400)
commit1d78e94abad9f32a1f08c75a5afb3028db71cf0c
tree1a2b5826d92e13bfae2232ef0c5c13000a966648tree | snapshot
parent3bf13893ab85fb912c0f54f147a98736fb2aa414commit | diff
azure/gitlab/travis: Add RISC-V SPL testing

This adds QEMU RISC-V 32/64 SPL testing. Unlike QEMU RISC-V 32/64,
we test SPL running in M-mode and U-Boot proper running in S-mode,
with a 4-core SMP configuration.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
.azure-pipelines.yml diff | blob | history
.gitlab-ci.yml diff | blob | history
.travis.yml diff | blob | history
"Das U-Boot" Source Tree.