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(parent: 4efdc48) | patch
feat(versal-net): add support for Xilinx Versal NET platform
authorMichal Simek <michal.simek@amd.com>
Wed, 31 Aug 2022 14:45:14 +0000 (16:45 +0200)
committerMichal Simek <michal.simek@amd.com>
Tue, 20 Sep 2022 07:19:43 +0000 (09:19 +0200)
commit1d333e69091f0c71854a224e8cfec08695b7d1f3
tree3564d74ce7775b5cc6e0b14ef7e788747d82be67tree | snapshot
parent4efdc488961502033262613b6f20abcee68bbf84commit | diff
feat(versal-net): add support for Xilinx Versal NET platform

New SoC is a78 based with gicv3 and uart over pl011. Communication
interfaces are similar to Versal platform. System starts with Xilinx PLM
firmware which loads TF-A(bl31) to DDR, which is already configured, and
jumps to it. PLM also prepare handoff structure for TF-A with information
what components were load and flags which indicate which EL level SW should
be started.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: I2a16c242a77be6c91be3d198727dc3b9bbb97410
12 files changed:
plat/xilinx/versal_net/aarch64/versal_net_common.c [new file with mode: 0644] blob
plat/xilinx/versal_net/aarch64/versal_net_helpers.S [new file with mode: 0644] blob
plat/xilinx/versal_net/bl31_versal_net_setup.c [new file with mode: 0644] blob
plat/xilinx/versal_net/include/plat_macros.S [new file with mode: 0644] blob
plat/xilinx/versal_net/include/plat_private.h [new file with mode: 0644] blob
plat/xilinx/versal_net/include/platform_def.h [new file with mode: 0644] blob
plat/xilinx/versal_net/include/versal_net_def.h [new file with mode: 0644] blob
plat/xilinx/versal_net/plat_psci.c [new file with mode: 0644] blob
plat/xilinx/versal_net/plat_topology.c [new file with mode: 0644] blob
plat/xilinx/versal_net/platform.mk [new file with mode: 0644] blob
plat/xilinx/versal_net/sip_svc_setup.c [new file with mode: 0644] blob
plat/xilinx/versal_net/versal_net_gicv3.c [new file with mode: 0644] blob
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