]> git.baikalelectronics.ru Git - kernel.git/commit
RISC-V: KVM: make CY, TM, and IR counters accessible in VU mode
authorMayuresh Chitale <mchitale@ventanamicro.com>
Mon, 31 Jan 2022 11:03:07 +0000 (16:33 +0530)
committerAnup Patel <anup@brainfault.org>
Wed, 2 Feb 2022 13:27:10 +0000 (18:57 +0530)
commit1c672fd5d447fdccb64120274eea8e7c0995dd2a
treec117b1965faee627f35a6f8d73d7fffbc2c85e73
parente3d921760f7d264aec2ce7b1af503363f8f3ce6f
RISC-V: KVM: make CY, TM, and IR counters accessible in VU mode

Those applications that run in VU mode and access the time CSR cause
a virtual instruction trap as Guest kernel currently does not
initialize the scounteren CSR.

To fix this, we should make CY, TM, and IR counters accessibile
by default in VU mode (similar to OpenSBI).

Fixes: ab2bb440d3a23 ("RISC-V: KVM: Implement VCPU create, init and
destroy functions")
Cc: stable@vger.kernel.org
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
arch/riscv/kvm/vcpu.c