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(parent: 9e040c0) | patch
clk: sunxi: mod1 clock should modify it's parent
authorAndrea Venturi <ennesimamail.av@gmail.com>
Mon, 21 Mar 2016 16:10:38 +0000 (17:10 +0100)
committerMaxime Ripard <maxime.ripard@free-electrons.com>
Thu, 21 Apr 2016 22:29:21 +0000 (00:29 +0200)
commit1b769e1aa482905be8180d799c99ffde04439a2e
tree5c5bf867e6b491b5c2e408ab8c9191461e96c68ctree | snapshot
parent9e040c060409ae1d4819d6b851d92d4cb0ec819fcommit | diff
clk: sunxi: mod1 clock should modify it's parent

add CLK_SET_RATE_PARENT to modify the rate on clk upstream

Signed-off-by: Marcus Cooper <codekipper@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
drivers/clk/sunxi/clk-a10-mod1.c diff | blob | history
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