]> git.baikalelectronics.ru Git - kernel.git/commit
drm/i915/ringbuffer: exclude last 2 cachelines on 845g on all callpaths
authorMika Kuoppala <mika.kuoppala@linux.intel.com>
Mon, 29 Oct 2012 14:59:26 +0000 (16:59 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Sun, 11 Nov 2012 22:51:09 +0000 (23:51 +0100)
commit1b5c7b86345fb2d812e00bddfc64b513c81c5943
treedc514c52a0091c6212afd2a9d188e45f706c733c
parentd12787f72c8b73c5d3bc8de370fc52bbf158788c
drm/i915/ringbuffer: exclude last 2 cachelines on 845g on all callpaths

Make intel_render_ring_init_dri and intel_init_ring_buffer symmetrical
with regards of workaround introduced by:

commit 582be44354544b2725caca9d398fd0acc6e309d8
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Mon Apr 9 13:59:46 2012 +0100

    drm/i915/ringbuffer: Exclude last 2 cachlines of ring on 845g

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_ringbuffer.c